This application claims the priority benefit of Taiwan application serial no. 91100553, filed Jan. 16, 2002.
1. Field of Invention
The present invention relates to a structure of a semiconductor memory device and the fabrication thereof. More particularly, the present invention relates to a structure of a non-volatile memory and the fabrication thereof.
2. Description of Related Art
Non-volatile memory is widely used to store booting information in personal computers and in various electronic apparatuses since the data stored in a non-volatile memory does not disappear when the power is turned off.
In the family of non-volatile memory, the simplest one is namely the mask read-only memory (Mask ROM). A Mask ROM uses a MOS transistor as a memory cell and is programmed by implanting ions into the channels of selected memory cells to alter their threshold voltages and thereby to control their logic states (0/1). A Mask ROM cell comprises a substrate, two bit-lines, a polysilicon word-line crossing over the bit-lines and a channel region in the substrate under the word-line and between the bit-lines. The channel region represents a logic state xe2x80x9c0xe2x80x9d orxe2x80x9c1xe2x80x9d dependent on the presence or absence of the ions implanted.
Another type of non-volatile memory is the well-known electrically erasable programmable read-only memory (E2PROM), which conventionally comprises a floating gate and a control gate both made from polysilicon. When an E2PROM is being programmed or erased, appropriate biases are applied to the control gate and to the source/region to inject charges into the floating gate or to drive out charges from the floating gate. However, if there are defects in the tunnel oxide layer under the floating gate in a conventional flash memory, a leakage easily occurs in the memory cell and the reliability of the device is thus lowered.
To solve the leakage problem of a flash memory, a nitride charge-trapping layer is recently used to replace the polysilicon floating gate in the conventional flash memory. The nitride charge-trapping layer is usually disposed between two silicon oxide layers to form an oxide/nitride/oxide (ONO) composite layer, while the memory with a nitride charge-trapping layer is known as a xe2x80x9cnitride read-only memory (NROM)xe2x80x9d. In a NROM, the nitride charge-trapping layer is able to trap electrons so that the injected hot electrons do not distribute evenly in the charge-trapping layer, but are localized in a region of the charge-trapping layer near the drain with a Gaussian spatial distribution. Because the injected electrons are localized, the charge-trapping region is small and is less likely to locate on the defects of the tunnel oxide layer. A leakage therefore does not easily occur in the device. Moreover, since the electrons are localized in a region of the charge-trapping layer near the drain, the NROM is capable of storing two bits in one memory-cell. This is achieved by changing the direction of the current in the channel and thus varying the generating site and the injecting region of the hot electrons. Thus, a memory cell can be configured one of the four states, in which each of the two ends of the charge-trapping layer may have one group of electrons with a Gaussian spatial distribution or have zero electron trapped in it.
However, when the non-volatile memory device is scaled down, the width of the bit-line of the non-volatile memory is also decreased. Therefore, the resistance of the bit-line becomes higher, which means that the xe2x80x9cbit-line loadingxe2x80x9d is higher.
To lower the resistance of the bit-line, a deeper junction or a higher dopant concentration is adopted in the prior art. However, a deeper junction will cause a severer short channel effect (SCE) and a larger punch-through leakage, and the dopant concentration of the bit-line is restricted by the solid-state solubility of the dopants. Therefore, miniaturizing the non-volatile memory device is still not easy.
Accordingly, this invention provides a non-volatile memory and the fabrication thereof to lower the bit-line loading in a miniaturized memory device.
To fabricate the non-volatile memory of this invention, a planar doped region is formed in a substrate. A mask layer and a patterned photoresist layer are sequentially formed on the substrate. A plurality of trenches are formed in the substrate with the photoresist layer as a mask to divide the planar doped region into a plurality of buried bit-lines. The photoresist layer is removed and then a recovering process may be performed to recover the side-walls and the bottoms of the trenches from the damages caused by the trench etching step. The mask layer is removed. A dielectric layer is formed on the substrate and then a plurality of word-lines are formed on the dielectric layer.
This invention also provides a method for fabricating a Mask ROM. In this method, a plurality of buried bit-lines and a plurality of word-lines are fabricated by the same method described above, and a gate dielectric layer is formed under the word-lines, while a portion of the substrate under the word-lines and between the buried bit-lines serves as a plurality of coding regions. Thereafter, a coding mask not covering selected coding regions is formed over the substrate and then a coding implantation is performed with the coding mask as a mask.
This invention also provides a method for fabricating a nitride read-only memory (NROM). In this method, a plurality of buried bit-lines and a plurality of word-lines are fabricated by the same method described above, but a charge trapping layer, instead of the (gate) dielectric layer mentioned above, is formed under the word-lines.
This invention further provides a non-volatile memory, which comprises a substrate, a plurality of buried bit-lines, a plurality of word-lines, and a dielectric layer. The buried bit-lines are located in the substrate and are separated by a plurality of isolating structures. The word-lines are disposed on a portion of the substrate and the isolating structures and cross over the isolating structures and the buried bit-lines. The dielectric layer is between the substrate and the word-lines. The isolating structures may comprise trenches.
In the method of fabricating a non-volatile memory, a Mask ROM or a NROM of this invention, the recovering process is used to rearrange the distorted lattice of the substrate caused by the etching process for forming the trenches. Consequently, the defects in the channel regions are reduced and a leakage is prevented.
Since the buried bit-lines are separated by the trenches, a deeper junction can be formed to lower the resistance of the buried bit-lines and thereby to lower the bit-line loading without adversely augmenting the short channel effect and the punch-through leakage.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.